In this letter, a multiuser cooperative network with multiple relays is introduced, and two decode-and-forward (DF) cooperation schemes are proposed aiming at outage-optimal and fair user scheduling, respectively. The outage probability and asymptotic expressions of symbol error probability (SEP) are derived to evaluate these two schemes. Analysis and simulations show that both schemes can achieve full diversity order, which is the combination of cooperative diversity and multiuser diversity.

Compiler is the most important supporting tool to facilitate the use of reconfigurable computing architecture (RCA). In this paper, a template-based compiler framework is proposed. This compiler can synthesize the executables for RCA from native high-level programming language source code directly. It supports to generate run-time dynamic configuration context. And it is capable to generate both full configuration context and partial configuration context. Experimental results show that the executables generated by the proposed compiler can achieve better execution performance and smaller configuration context size than previous compilers. Moreover, this compiler does not require the programmer to have any extra knowledge about the hardware architecture of RCA.

This paper presents a novel architecture design to optimize the reconfiguration process of a coarse-grained reconfigurable architecture (CGRA) called Reconfigurable Multimedia System II ( REMUS-II ). In REMUS-II, the tasks in multi-media applications are divided into two parts: computing-intensive tasks and control-intensive tasks. Two Reconfigurable Processor Units (RPUs) for accelerating computing-intensive tasks and a Micro-Processor Unit (µPU) for accelerating control-intensive tasks are contained in REMUS-II. As a large-scale CGRA, REMUS-II can provide satisfying solutions in terms of both efficiency and flexibility. This feature makes REMUS-II well-suited for video processing, where higher flexibility requirements are posed and a lot of computation tasks are involved. To meet the high requirement of the dynamic reconfiguration performance for multimedia applications, the reconfiguration architecture of REMUS-II should be well designed. To optimize the reconfiguration architecture of REMUS-II, a hierarchical configuration storage structure and a 3-stage reconfiguration processing structure are proposed. Furthermore, several optimization methods for configuration reusing are also introduced, to further improve the performance of reconfiguration process. The optimization methods include two aspects: the multi-target reconfiguration method and the configuration caching strategies. Experimental results showed that, with the reconfiguration architecture proposed, the performance of reconfiguration process will be improved by 4 times. Based on RTL simulation, REMUS-II can support the 1080p@32 fps of H.264 HiP@Level4 and 1080p@40 fps High-level MPEG-2 stream decoding at the clock frequency of 200 MHz. The proposed REMUS-II system has been implemented on a TSMC 65 nm process. The die size is 23.7 mm2 and the estimated on-chip dynamic power is 620 mW.

A coarse-grained reconfigurable architecture (CGRA) is typically hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many computation-intensive kernels (e.g., loop nests) are often mapped onto RPUs to speed up the execution of programs. Thus, mapping optimization of loop nests is very important to improve the performance of CGRA. Processing element (PE) utilization rate, communication volume and reconfiguration cost are three crucial factors for the performance of RPUs. Loop transformations can affect these three performance influencing factors greatly, and would be of much significance when mapping loops onto RPUs. In this paper, a joint loop transformation approach for RPUs is proposed, where the PE utilization rate, communication cost and reconfiguration cost are under a joint consideration. Our approach could be integrated into compilers for CGRAs to improve the operating performance. Compared with the communication-minimal approach, experimental results show that our scheme can improve 5.8% and 13.6% of execution time on motion estimation (ME) and partial differential equation (PDE) solvers kernels, respectively. Also, run-time complexity is acceptable for the practical cases.

In this paper, a robust fractional order memory polynomial pre-distorter with two novel schemes to conduct digital base-band power amplifier pre-distortion is proposed. For the first scheme, fractional order terms are included in the conventional memory polynomial containing the odd and even order polynomial terms, which is called Scheme One. The second scheme, called Scheme Two, simply replaces even order polynomial terms with fractional order polynomial terms to improve the linear performance of power amplifiers. The mathematical expressions for these two schemes are derived. The computer simulations and numerical analysis show that, compared with the conventional pre-distortion methods, 11 dB and 8.5 dB more out-of-band suppression gain can be obtained by Scheme One and Scheme Two, respectively. Corresponding FPGA realization shows that the two schemes are cost-effective in terms of hardware resources.

Video Up-scaling is a hotspot in TV display area; as an important brunch of Video Up-scaling, Texture-Based Video Up-scaling (TBVU) method shows great potential of hardware implementation. Coarse-grained Reconfigurable Architecture (CGRA) is a very promising processor; it is a parallel computing platform which provides high performance of hardware, high flexibility of software, and dynamical reconfiguration ability. In this paper we propose an implementation of TBVU on CGRA. We fully exploit the characters of TBVU and utilize several techniques to reduce memory I/O operation and total execution time. Experimental results show that our work can greatly reduce the I/O operation and the execution time compared with the non-optimized ones. We also compare our work with other platforms and find great advantage in execution time and resource utilization rate.

This letter presents two constructions of Gaussian integer Z-periodic complementary sequences (ZPCSs), which can be used in multi-carriers code division multiple access (MC-CDMA) systems to remove interference and increase transmission rate. Construction I employs periodic complementary sequences (PCSs) as the original sequences to construct ZPCSs, the parameters of which can achieve the theoretical bound if the original PCS set is optimal. Construction II proposes a construction for yielding Gaussian integer orthogonal matrices, then the methods of zero padding and modulation are implemented on the Gaussian integer orthogonal matrix. The result Gaussian integer ZPCS sets are optimal and with flexible choices of parameters.

In this correspondence, two types of multiple binary zero correlation zone (ZCZ) sequence sets with inter-set zero cross-correlation zone (ZCCZ) are constructed. Based on orthogonal matrices with order N×N, multiple binary ZCZ sequence sets with inter-set even and odd ZCCZ lengthes are constructed, each set is an optimal ZCZ sequence set with parameters (2N2, N, N+1)-ZCZ, among these ZCZ sequence sets, sequences possess ideal cross-correlation property within a zone of length 2Z or 2Z+1. These resultant multiple ZCZ sequence sets can be used in quasi-synchronous CDMA systems to remove the inter-cell interference (ICI).

Graph sampling is an effective method to sample a representative subgraph from a large-scale network. Recently, researches have proven that several classical sampling methods are able to produce graph samples but do not well match the distribution of the graph properties in the original graph. On the other hand, the validation of these sampling methods and the scale of a good graph sample have not been examined on weighted graphs. In this paper, we propose the weighted graph sampling problem. We consider the proper size of a good graph sample, propose novel methods to verify the effectiveness of sampling and test several algorithms on real datasets. Most notably, we get new practical results, shedding a new insight on weighted graph sampling. We find weighted random walk performs best compared with other algorithms and a graph sample of 20% is enough for weighted graph sampling.

In this letter, based on orthogonal Golay sequence sets and orthogonal matrices, general constructions of zero correlation zone (ZCZ) aperiodic complementary sequence (ZACS) sets are proposed. The resultant ZACSs have column sequence peak-to-mean envelop power ratio (PMEPR) of at most 2, and the parameters of the sequence sets are optimal with respect to the theoretical bound. The novel ZACS sets are suitable for approximately synchronized multi-carrier CDMA (MC-CDMA) communication systems.

We show a tracking attack against the newest ID-transfer scheme for low-cost RFID tags. In this attack, a wide attacker, i.e. an attacker that can access the verification result of a server, is able to forge a set of specific messages, and to track a tag. The attack is unique as it involves three sessions of the protocol. Finally, a simple feasibility analysis of the attack is given.

In this letter, we propose a supervised bimodal emotion recognition approach based on two important human emotion modalities including facial expression and body gesture. A effectively supervised feature fusion algorithms named supervised multiset canonical correlation analysis (SMCCA) is presented to established the linear connection between three sets of matrices, which contain the feature matrix of two modalities and their concurrent category matrix. The test results in the bimodal emotion recognition of the FABO database show that the SMCCA algorithm can get better or considerable efficiency than unsupervised feature fusion algorithm covering canonical correlation analysis (CCA), sparse canonical correlation analysis (SCCA), multiset canonical correlation analysis (MCCA) and so on.

The coarse-grained reconfigurable architecture (CGRA) is a promising computing platform that provides both high performance and high power-efficiency. The computation-intensive portions of an application (e.g. loop nests) are often mapped onto CGRA for acceleration. However, mapping loop nests onto CGRA efficiently is quite a challenge due to the special characteristics of CGRA. To optimize the mapping of loop nests onto CGRA, this paper makes three contributions: i) Establishing a precise performance model of mapping loop nests onto CGRA, ii) Formulating the loop nests mapping as a nonlinear optimization problem based on polyhedral model, iii) Extracting an efficient heuristic algorithm and building a complete flow of mapping loop nests onto CGRA (PolyMAP). Experiment results on most kernels of the PolyBench and real-life applications show that our proposed approach can improve the performance of the kernels by 27% on average, as compared to the state-of-the-art methods. The runtime complexity of our approach is also acceptable.

In this paper, we propose a preemptive priority handoff scheme for integrated voice/data cellular mobile systems. In our scheme, calls are divided into three different classes: handoff voice calls, originating voice calls, and data calls. In each cell of the system there is a queue only for data calls. Priority is given to handoff voice calls over the other two kinds of calls. That is, the right to preempt the service of data is given to a handoff voice call if on arrival it finds no idle channels. The interrupted data call returns to the queue. The system is modeled by a two-dimensional Markov chain. We apply the Successive Over-Relaxation (SOR) method to obtain the equilibrium state probabilities. Blocking and forced termination probabilities for voice calls are obtained. Moreover, average queue length and average transmission delay of data calls are evaluated. The results are compared with another handoff scheme for integrated voice/data cellular mobile systems where some numbers of channels are reserved for voice handoff calls. It is shown that, when the data traffic is not very light, the new scheme can provide lower blocking probability for originating voice calls, lower forced termination probability for ongoing voice calls, and shorter average queue length and less average transmission delay for data calls.

MDS transformation plays an important role in resisting against differential cryptanalysis (DC) and linear cryptanalysis (LC). Recently, M. Sajadieh, et al.[15] designed an efficient recursive diffusion layer with Feistel-like structures. Moreover, they obtained an MDS transformation which is related to a linear function and the inverse is as lightweight as itself. Based on this work, we consider one specific form of linear functions to get the diffusion layer with low XOR gates for the hardware implementation by using temporary registers. We give two criteria to reduce the construction space and obtain six new classes of lightweight MDS transformations. Some of our constructions with one bundle-based LFSRs have as low XOR gates as previous best known results. We expect that these results may supply more choices for the design of MDS transformations in the (lightweight) block cipher algorithm.

In this letter, a construction of asymmetric Gaussian integer zero correlation zone (ZCZ) sequence sets is presented based on interleaving and filtering. The proposed approach can provide optimal or almost optimal single Gaussian integer ZCZ sequence sets. In addition, arbitrary two sequences from different sets have inter-set zero cross-correlation zone (ZCCZ). The resultant sequence sets can be used in the multi-cell QS-CDMA system to reduce the inter-cell interference and increase the transmission data.

Based on sample-pair refinement and local optimization, this paper proposes a high-accuracy and quick matting algorithm. First, in order to gather foreground/background samples effectively, we shoot rays in hybrid (gradient and uniform) directions. This strategy utilizes the prior knowledge to adjust the directions for effective searching. Second, we refine sample-pairs of pixels by taking into account neighbors'. Both high confidence sample-pairs and usable foreground/background components are utilized and thus more accurate and smoother matting results are achieved. Third, to reduce the computational cost of sample-pair selection in coarse matting, this paper proposes an adaptive sample clustering approach. Most redundant samples are eliminated adaptively, where the computational cost decreases significantly. Finally, we convert fine matting into a de-noising problem, which is optimized by minimizing the observation and state errors iteratively and locally. This leads to less space and time complexity compared with global optimization. Experiments demonstrate that we outperform other state-of-the-art methods in local matting both on accuracy and efficiency.

As technology moves to 600-1000 Gb/sq-in areal densities and deep sub-10 nm head-disk spacing, it is of crucial importance to prevent both the conventionally defined thermal decay and the tribologically induced decay of recorded magnetic signal. This paper reports a novel method for recording and visualizing the signature of the potential tribological decay. The details of the methodology, its working principles, and typical results obtained are presented in this work. The method is based on the introduction of a type of visualizing disks which use a layer of magneto-optical material with low Curie temperature to replace the magnetic layer used in the conventional magnetic media. The method and corresponding setup were used successfully in the visualization of potential decay caused by slider-particle-disk contact, slider-disk contact during track seeking operations, and slider-disk impact during loading and unloading operations.

This paper presents a self-clustering algorithm to detect symmetry in images. We combine correlations of orientations, scales and descriptors as a triple feature vector to evaluate each feature pair while low confidence pairs are regarded as outliers and removed. Additionally, all confident pairs are preserved to extract potential symmetries since one feature point may be shared by different pairs. Further, each feature pair forms one cluster and is merged and split iteratively based on the continuity in the Cartesian and concentration in the polar coordinates. Pseudo symmetric axes and outlier midpoints are eliminated during the process. Experiments demonstrate the robustness and accuracy of our algorithm visually and quantitatively.

Future high density magnetic recording requires a nanometer spaced head-slider interface, high track seeking velocity and high spindle speed. Such a combination greatly increases the likelihood of slider-disk and slider-particle-disk impact. Furthermore, the impact can generate high flash temperature and leads to data reliability problems, such as partial or full data erasure. This work report a method to conduct controlled experimental investigations into the possibility of such a data erasure even when the temperature is far below the Curie temperature. Results indicate that the high density magnetic transitions are of high likelihood of being affected by the flash temperature. Investigations also extended to micromagnetic modeling of the flash temperature effect. Results suggest that thermally induced local stress can play important roll in the data erasure process. Modeling results also exhibit that smaller grain size and higher recording density are also of higher likelihood of getting the transitions being affected by the flash temperature.